1. Field
Example embodiments of the inventive concepts relate to a method for wafer level packaging and a semiconductor device fabricated using the same, and more particularly, to a wafer level package module and a semiconductor device manufactured using the same, which can package a plurality of semiconductor chips at a wafer level.
2. Description of the Related Art
In recent years, studies on packages of semiconductor integrated circuits have advanced to chip-size packages that can reduce the size of packages to a semiconductor chip level while maintaining the characteristics of a bare chip. Regarding chip size packages, forming of solder balls after a chip pad is rewired in a chip surface is called a wafer level chip size package. In the wafer level chip size package, chips are directly mounted in a circuit board by a manner called a flip chip, and the solder balls formed on the rewired circuit of a chip are coupled to a conductive pad of the circuit board. Semiconductor chips comprising image sensors such as Charge Coupled Devices (CCD) and Complementary Metal-Oxide Semiconductors (CMOS) are being packaged with glass at an upper portion.